1. Field of the Invention
The present invention relates to a control circuit for a computer system and, more particularly to a control circuit for inhibiting the clock input to a central processing unit (CPU) during power-up conditions until the power supply voltage has stabilized which also provides a delayed signal to the reset circuitry to enable the CPU to be consistently reset after power-up once the inhibit to the clock signal is removed.
2. Description of the Prior Art
All CPUs have a CLOCK input that controls the timing of the CPU, as well as the transfer of data relative to its data and address buses. In a typical CPU, the CLOCK input is tied to an internal phase-locked-loop (PLL) that is normally used to create a new timing reference; normally a multiple of the frequency of the CLOCK input. Heretofore, during power-up conditions, no restrictions have been known to be placed on the input CLOCK signal to the CPU. However, problems have developed with the newer submicron CPU architectures, such as the Intel 80486 DX. In particular, with such CPUs, problems have occurred when the CLOCK input has been allowed to toggle before the power supply voltage has been stabilized. Such problems include a "locking-up" condition believed to occur as a result of the CLOCK input toggling during power-up which causes as is internal PLL to get into an illegal condition causing the system to hang up. As such, when such a condition occurs, the power supply must be switched off and then back on in order to attempt to reboot the system. This problem is best illustrated with reference to FIG. I wherein, three waveforms 28, 30 and 32 are illustrated, shown in graphical form where the horizontal axis represents time or clock cycles and the vertical axis represents magnitude of the respective waveforms. The waveform 28 represents an inactive RESET signal; representing a running condition. The waveform 30 is a representation of an ADS signal, normally used by the CPU to indicate a valid address on the address bus. As shown, the ADS signal is shown in an error condition. In particular, as discussed above, during a condition when the CLOCK input is allowed to toggle during power-up, an internal PLL goes into an illegal condition, which in turn, causes the ADS signal to be generated as an error pulse 34. Since the various circuits within the computer system, such as the memory controller are synchronous and are only able to read data on rising CLOCK edges, other circuitry within the computer system and, in particular, the memory controller is unable to read the ADS error signal since the pulse 34 occurs prior to the next successive clock edge 36. As such, the memory controller indefinitely awaits an ADS signal so that it can send a handshake READY signal back to the CPU. Since the memory controller does not see the error pulse 34, the system hangs up.
Various attempts have been made to resolve this problem. For example, FIGS. 2-4 show various methods to suppress the CLOCK input during power-up. Referring to FIG. 2. a control circuit, generally identified with the reference numeral 20, is illustrated for inhibiting the CLOCK input to the CPU. The circuit consists of a transistor 22 and a resistor 24. The circuitry 20 functions to suppress or inhibit the output of an oscillator 26 during power-up conditions. In particular, the output of the oscillator 26 is applied to the CLOCK input of the CPU. During power-up conditions, the output of the oscillator 26 is connected to ground by way of the transistor 22. The transistor 22 is under the control of a POWERGOOD signal available from the power supply. The POWERGOOD signal is normally high when the output voltage of the power supply (i.e., V.sub.cc) has stabilized. Thus, during power-up conditions, the POWERGOOD signal is low. This low POWERGOOD signal tums the transistor 22 on to effectively ground the output of the oscillator 26 during power-up conditions. Once the output voltage of the power supply stabilizes, the POWERGOOD signal goes high which, in turn, rams off the transistor 22 to effectively remove the inhibit froill the output of the oscillator 26.
FIGS. 3 and 4 illustrate other known circuits used to inhibit the CLOCK input to the CPU during power-up conditions. Referring first to FIG. 3, the output of the oscillator 26 is ANDed with the POWERGOOD signal by way of an AND gate 38. The output of the AND gate 38, in turn, is applied to the CLOCK input of the CPU. During power-up conditions, the POWERGOOD signal is low which effectively disables the output of the oscillator 26 until the output voltage of the power supply has stabilized. The circuitry in FIG. 4 is similar except that a relay 40 is used. In that circuit, tile output or the oscillator 26 is connected in series with a set of contacts (not shown) from the relay 40. The contacts, in turn, are connected to the CLOCK input of the CPU. The relay 40 is under the control of either the power supply voltage V.sub.cc or the POWERGOOD signal. In particular, either the power slippery voltage V.sub.cc or the POWERGOOD signal is applied to the coil (not shown) of the relay 40. Since such coils normally have a minimum pickup voltage, the oscillator 26 would effectively be disconnected from the CLOCK input of the CPU during power-up conditions since either a low POWERGOOD signal or the power supply voltage V.sub.cc voltage being less than the picktip voltage of the relay 40 would keep the relay 40 from being energized during such a condition which, in turn, would keep the contacts from closing to enable the output of the oscillator 26 from being applied to the CLOCK input of the CPU.
Although the control circuits illustrated in FIGS. 2-4 is effective to inhibit the CLOCK input to the CPU until the power supply voltage V.sub.cc has stabilized, there are other problems attendant with the use of such circuits. In particular, such control circuits do not address the problem regarding the system reset during power-up conditions. More particularly, during power-up conditions, the CPU is normally reset to force the CPU and, in particular, the internal registers therewithin to a known state. The RESET signal is normally generated externally to the CPU, for example, by a memory controller which may be an Intel Model No. 82424TX. Normally, a RESET signal is normally generated by the bus controller within a few clock cycles anew power-up in order to reset the CPU to a known state. However, the generation of the RESET signal after a power-up has been inconsistent when known circuits, such as those illustrated in FIGS. 2-4 are used. Examples of such inconsistent results utilizing prior art circuitry as discussed above is illustrated in FIGS. 5 and 6. In particular, FIGS. 5 and 6 illustrate known waveforms 58, 60 and 62 for the POWERGOOD, RESET and CLOCK signals, respectively, during a power-up condition utilizing prior an control circuits, such as the circuits illustrated in FIGS. 2-4 which inhibit the CLOCK input of the CPU until the power supply voltage V.sub.cc has stabilized. Referring first to FIG. 5, during the time period T.sub.1, the power supply voltage V.sub.cc is stabilizing. During this time period, the POWERGOOD signal is low, which, in turn, inhibits the CLOCK waveform 62 as shown. As mentioned above, the circuitry for the RESET waveform 60 is synchronous circuitry and, therefore, requires a CLOCK input for proper operation. Therefore, during the time period T.sub.1, the RESET signal is active high, maintaining the system in a RESET condition. At time period T.sub.1, the power supply voltage V.sub.cc stabilizes and causes a transition of the POWERGOOD signal, forcing that signal to go high. As mentioned above, once the POWERGOOD signal goes high, the inhibit is removed from the CLOCK input to enable periodic clock pulses 64 to be fed into the CLOCK input of the CPU, as well as the bus controller. Ideally, within a predetermined number of CLOCK cycles after the inhibit of the CLOCK input is removed, the reset circuitry within the bus controller forces the RESET signal low to remove the system RESET and enable the CPU to boot. However, as illustrated in FIG. 5, the active high RESET waveform 60 remains high, keeping the system in RESET and forcing the user to switch the power supply off and then back on, and attempt to reboot the system.
FIG. 6 illustrates an example where the RESET signal was properly cleared after a predetermined number of CLOCK cycles once the power supply voltage V.sub.cc stabilized. Similar to FIG. 5, the power supply stabilizes at time T.sub.t causing the POWERGOOD signal 58 to transition from a low to a high. As mentioned above, the high POWERGOOD signal removes the inhibit from the CLOCK input of the CPU to cause periodic CLOCK pulses 64 to be applied to the CLOCK input. On this trial, the RESET signal was properly cleared within a predetermined number of CLOCK cycles after the time T.sub.1. In particular, with reference to the waveform 60, the RESET signal transitions from an active high to a low condition at time T.sub.2. During this trial, the RESET signal was cleared by the bus controller in order to enable the system to boot in the normal sequence.
The circuitry illustrated in FIGS. 2-4 is adapted to disable the CLOCK input to the CPU until the power supply voltage V.sub.cc is stabilized (i.e., POWERGOOD goes high). However, these circuits do not address the problem relating to the reset circuitry as discussed above and, further, create an additional problem. In particular, the circuits illustrated in FIGS. 3 and 4 both utilize components 38 and 40 in-line between the oscillator 26 and the CLOCK input to the CPU. These components 38 and 40 add a delay to the output CLOCK signals from the oscillator 26. Since it is known to use various CLOCK signals within a computer system, the delay of the signals to the CLOCK input to the CPU would cause the CPU timing to be out of time with respect to other related devices which are driven directly by the oscillator 26; for example, a bus controller.